Fetch-Decode-Execute Cycle

An example of the CPU decoding an instruction as part of the Fetch-Decode-Execute cycle:

Example: Adding Two Numbers

1. Fetch:

   • Program Counter (PC): The PC holds the address of the next instruction to be executed. For this example, let’s assume the PC points to the memory address where the ADD R1, R2, R3 instruction is stored.
   • Memory Address Register (MAR): The address from the PC is loaded into the MAR.
   • Memory Data Register (MDR): The instruction at the address in the MAR is fetched from memory and loaded into the MDR.
   • Instruction Register (IR): The fetched instruction (ADD R1, R2, R3) is then transferred from the MDR to the IR.
   • Program Counter (PC): The PC is incremented to point to the next instruction in memory.

2. Decode:

   • Control Unit (CU): The CU reads the instruction from the IR. It identifies the opcode (ADD) and the operands (R1, R2, R3).
   • Opcode Decoding: The CU decodes the opcode to determine that an addition operation is required.
   • Operand Fetching: The CU fetches the values stored in registers R2 and R3. Let’s assume R2 contains the value 5 and R3 contains the value 10.
   • Control Signals: The CU generates the necessary control signals to perform the addition operation in the ALU.

3. Execute:

   • Arithmetic Logic Unit (ALU): The ALU receives the control signals and the operand values (5 and 10).
   • Addition Operation: The ALU performs the addition: 5 + 10 = 15.
   • Result Storage: The result (15) is stored in register R1.

Detailed Steps in Decoding:

• Instruction Register (IR): Holds the fetched instruction.
• Control Unit (CU): Decodes the instruction by interpreting the opcode (operation code) and determining the required operation.
• Control Signals: Generated by the CU to direct the ALU and other parts of the CPU to perform the operation.

Example in Binary:

• Suppose the binary representation of ADD R1, R2, R3 is 0001 0010 0011 0001.
  • 0001 (opcode for ADD)
  • 0010 (R2)
  • 0011 (R3)
  • 0001 (R1)

During the decode phase, the CU interprets 0001 as the ADD operation and identifies 0010, 0011, and 0001 as the registers involved.

Visual Representation:

1. Fetch:

   • Memory Address Register (MAR): Points to the memory location of the instruction.
   • Memory Data Register (MDR): Fetches the instruction and places it in the IR.

2. Decode:

   • Control Unit (CU): Decodes the instruction in the IR.
   • Control Signals: Generated based on the opcode and operands.

3. Execute:

   • Arithmetic Logic Unit (ALU): Performs the addition.
   • Result Storage: The result is stored in the specified register.

This cycle repeats for each instruction in the program, allowing the CPU to perform complex tasks by breaking them down into simple operations.

https://www.youtube.com/watch?v=pogNgsKnfU0